1. Field of the Invention
This invention relates, generally, to solid state load protection systems and more particularly to an inverse time delay circuit enabling a load protection system to accurately respond to an overload condition in a time which is inversely related to the percent of overload current.
2. Description of the Prior Art
It is known that some load protection systems have various protection functions such as current overload, phase loss, and ground fault sensing. These functions generally provide a trip time for a circuit breaker and associated load which is inversely related to the square of the current flowing in the load to be protected. Therefore, an inverse time relationship is generally utilized whereby the time between a fault which is sensed and trip out are inversely related such that a high overcurrent will result in a very short period of time for device trip out and a relatively low overcurrent fault will result in a substantially longer time before trip out. Types of devices which accomplish the above can be found in U.S. Pat. No. 4,021,703, "Phase Imbalance Detection Circuit", issued May. 3, 1977 to Gary, et al; U.S. Pat. No. 3,996,499, "Zener Diode Effect on Long Acceleration Module", issued Dec. 7, 1976 to Gary, et al.; U.S. Pat. No. 3,818,275, "Circuit Interrupter Including Improved Trip Circuit Using Current Transformers", issued June 18, 1974 to Shimp and U.S. Pat. No. 3,602,783, "Circuit Breaker Device Including Improved Overcurrent Protection Device", issued Aug. 31, 1971 to Engle, et al., all assigned to the assignee of the present invention. However, in the above-mentioned patents during a high current overload condition, the time before trip-out may not be sufficiently brief to ensure optimum load protection. Additionally the time before initiating a trip-out during an overload condition may be unfavorably influenced by stray signals in the associated circuitry.
It is desirable to have an inverse time delay circuit which responds accurately and uniformly to high current overload conditions. It is also desirable to have an inverse time delay circuit which minimizes the effect of stray and therefore erroneous signals which may be present in the associated circuitry.